The present invention relates to a memory test apparatus, and in particular, to a memory test apparatus stuitable to test a high-performance memory having at least two memory functions.
Large-scale integration (LSI) memory devices have been developed in various fashions, for example, the memory capacity has been increased to 256K bits or 1M bits, the nibble mode has been introduced for a higher-speed operation, and a two-port configuration has been implemented in a video random access memory (RAM) for an improved performance.
Marching and galloping patterns are well known as test patterns for a semiconductor memory. These patterns are generated by use of an algorithmic pattern generator. As shown in FIG. 3, as a memory IC begins to have higher performance, two kinds of memory functions are contained in the same chip. A memory unit B configured with a shift register is called a video RAM, which is used to process images. While a great amount of image data is read or written by use of an address 6 of a memory unit A and input/output data 7 and 10, display data to a cathode-ray tube (CRT) is transferred from the memory unit A via a signal line 4 so as to be read at a high speed synchronized with the display speed of the CRT. During a read operation on the memory unit B, data access is independently achieved on the memory unit A. Such memory functions require a memory tester to effect an independent test for the memory units A and B, and to have a capability of checking the data transfer function therebetween. That is, when data algorithmically written in the memory unit A is read in column or row units and is transferred to the memory unit (shift register) B so as to sequentially read the data through an output data line 11, the relationships between the preceding and succeeding data thus read are no longer algorithmic; consequently known prior art testers cannot generate the data expected for checking the memory. Moreover, the operation speeds of the large-capacity, low-speed memory unit A and that of the small-capacity, high-speed memory unit (register) B are different from each other. In addition, these memory units A and B must be synchronized only when data is transferred therebetween.
An apparatus of this kind has been described in "Testing a 317K Bit High Speed Video Memory with a VSLI Test System" (1984 ITC.P., pp. 294-299). In this example, however, a CCD memory is an objective item, and hence the system is not directly related to the present invention. Although a method for testing a video memory has been described, the configuration of the system has not been discussed.
In another example of an LSI memory test apparatus described in "Optimizing the Timing Architechture of a Digital LSI Test System", 1983 IEEE Int. Test Conf. paper 8.5, pp. 200-209, an external synchronization function is added to a timing signal generator to test an LSI having an integrated oscillation circuit or a minor cycle is further included in an operation cycle (test cycle) of the test apparatus to test an LSI having a clock demultiplier therein, namely, a minor cycle test cycle generator is provided in a timing generator to increase the test efficiency.
In these conventionl apparatuses, however, test provisions have not been considered with respect to such LSI's as a dual port memory of a multiprocessor or an image memory in which a plurality of data items are communicated in an asynchronous fashion, and hence these memory units cannot be tested in an actual operating state.
In addition, a video memory has been described in "320 Rows.times.700 Columns Image Dedicated Serial Input/Output Dynamic Memory for TV or VTR Field Memory" (Nikkei Electronics, Feb. 11, 1985); however, the configuration of the host system has not been discussed.